Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.
Keywords: FPAA, Simulink, reconfigurable analog, neuromorphic engineering
Citation: Hasler J and Marr B (2013) Finding a roadmap to achieve large neuromorphic hardware systems. Front. Neurosci. 7:118. doi: 10.3389/fnins.2013.00118
Received: 04 April 2012; Accepted: 20 June 2013;
Published online: 10 September 2013.
Edited by:Gert Cauwenberghs, University of California, San Diego, USA
Reviewed by:Bernabe Linares-Barranco, Instituto de Microelectrónica de Sevilla, Spain
Copyright © 2013 Hasler and Marr. This is an open-access article distributed under the terms of the Creative Commons Attribution License (CC BY). The use, distribution or reproduction in other forums is permitted, provided the original author(s) or licensor are credited and that the original publication in this journal is cited, in accordance with accepted academic practice. No use, distribution or reproduction is permitted which does not comply with these terms.
*Correspondence: Jennifer Hasler, Georgia Institute of Technology, Atlanta, GA 30332-250, USA e-mail: email@example.com
†Present address: Bo Marr, Raytheon Segundo, CA, USA